1. Field of the Invention
The present invention relates to a structure of a semiconductor memory device (particularly, nonvolatile memory) having a laminated gate structure and a method of manufacturing the same.
2. Description of the Related Art
In a semiconductor memory device having a laminated gate structure, contacts have heretofore been provided at intersecting points of active region columns and active region rows, respectively. Incidentally, the active region columns correspond to an active region extending in a first direction, whereas the active region rows correspond to an active region extending in a second direction substantially orthogonal to the first direction.
FIGS. 3-1 and 3-2 are respectively diagrams showing structures of such a conventional semiconductor memory device. A description will be made here of a nonvolatile memory having floating gates as the semiconductor memory device FIG. 3-1(a) shows a planar structure of a memory cell of the nonvolatile memory, FIG. 3-1(b) shows a sectional structure of the memory cell, which is taken along line A-A′ shown in FIG. 3-1(a), and FIG. 3-1(c) shows a-sectional structure of the memory cell, which is taken along line B-B′ shown in FIG. 3-1(a), respectively. FIG. 3-2(a) illustrates a planar structure of the memory cell of the nonvolatile memory, and FIG. 3-2(b) depicts an equivalent circuit of the nonvolatile memory shown in FIG. 3-2(a), respectively. The semiconductor memory device having such a structure has been disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 1 (1989)-181572 (patent document 1).
As shown in FIG. 3-1, an active region 101 and device isolation regions 102 are formed within a silicon substrate 100. Incidentally, the active region 101 comprises a plurality of active region columns 52 extending in a first direction (corresponding to a vertical direction as viewed in FIG. 3-1), and a plurality of active region rows 53 extending in a second direction (corresponding to a horizontal direction as viewed in FIG. 3-1) substantially orthogonal to the first direction. The active region 101 and the device isolation regions 102 are formed with the boundaries of their side surfaces aslant as shown in FIG. 3-1(b) and FIG. 3-1(c) (In FIG. 3-1(a), however, only the upper surface portion of the active region 101 is shown and the boundaries of the slanted side surfaces of the active region 101 and the device isolation regions 102 are shown in an omitted form).
A first gate insulating film 107 is formed on its corresponding part of the active region 101 (see FIG. 3-1(a) and FIG. 3-1(c)).
A floating gate 103, which serves as each floating electrode, is formed on each of the first gate insulating film 107 and the device isolation regions 102 (see FIG. 3-1(a) and FIG. 3-1(c)). The floating gate 103 is a conductive film made principally of polysilicon doped with an impurity and is formed by the known CVD/photolitho/etching technology.
A control gate 104, which serves as each control electrode through the second gate insulating film 108, is formed on the device isolation regions 102 of between adjacent floating gates with on the floating gates and in the rows direction of the floating gates. (see FIG. 3-1(b) and FIG. 3-1(c))
A control gate 104, which serves as each control gate, is formed on its corresponding second gate insulating film 108 (see FIG. 3-1(a) and FIG. 3-1(c)). The control gate 104 is a conductive film principally made up of two-layer film polycide of polysilicon doped with an impurity and silicide and is formed by the known CVD/photolitho/etching technology. Incidentally, each control gate 104 serves even as a word line.
An interlayer insulating film 109 is formed on the control gate 104, the first gate insulating film 107, and the device isolation regions 102. An upper wiring 110 is formed on the interlayer insulating film 109. (see FIG. 3-1(b) and FIG. 3-1(c)).
Contacts 106, which extend through the interlayer insulating film 109 and make electrical connections between the active region 101 and the upper wiring 110 to be described later, are formed within the interlayer insulating film 109 (see FIG. 3-1(a) and FIG. 3-1(b)). The contacts 106 are formed by firstly forming contact holes extending through the interlayer insulating film 109 by the know CVD/photolitho/etching technology and then embedding a contact embedding material corresponding to a conductive substance into the contact holes. Incidentally, tungsten is principally used as the contact embedding material.
Further, the upper wiring 110 is formed on the interlayer insulating film 109 (see FIG. 3-1(b) and FIG. 3-1(c)). Incidentally, since FIG. 3-1(b) and FIG. 3-1(c) show configurations at the time that the contacts 106 have been formed, the upper wiring 110 formed subsequently is shown with a dotted line.
In such a conventional semiconductor memory device 51, the contacts 106 are respectively provided at intersecting points of the active region columns 52 and the active region rows 53 as shown in FIG. 3-1(a). If such a conventional semiconductor memory device 51 is shown in the form of functional components or constituent elements such as bit lines BL, word lines WL, source lines (called also source/drain) SL, etc., it is then represented as shown in FIG. 3-2(a). If the semiconductor memory device 51 is expressed in an equivalent circuit, it is then represented as shown in FIG. 3-2(b). Incidentally, the source lines SL correspond to portions that do not overlap the contacts 106 and the word lines WL in the active region 101. In FIG. 3-2(a), diagonally-shaped areas indicate fields. In such a conventional semiconductor memory device 51, the active region 101 is formed with the boundary between the side surfaces of the active region 101 and the device isolation region 102 aslant at the intersecting point of the active region column 52 and the active region row 53. In contrast, the active region 101 is vertically formed at a location (an intermediate point of line A-A′ in FIG. 3-1(a) by way of example) other than each intersecting point without slanting the boundary between the side surfaces of the active region 101 and the device isolation region 102. Therefore, each contact 106 provided at the intersecting point increases in area brought into contact with the active region 101 at the bottom as compared with the case in which the contact 106 provided at each intersection point is placed in the location (intermediate point of line A-A′ in FIG. 3-1(a) by way example) other than the intersecting point. Thus, the conventional semiconductor memory device enables a reduction in contact resistance.
Patent Document 1:
Japanese Unexamined Patent Publication No. Hei 1 (1989)-181572 (see FIGS. 1 through 6)
In the conventional semiconductor memory device, the contacts have been provided at the intersecting points of the active region columns 52 and the active region rows 53 respectively as described above.
In such a conventional semiconductor memory device, the part of first gate insulating film 107 is etched excessively when the floating gate 103 is patterned. The first gate insulating film 107 is etched when the floating gate is removed after the control gate 104 and the second gate insulating film 108 are patterned. The floating gate 103 is formed with polysilicon etc. Liquid into which polysilicon is easy to etch is used in etching process. The first gate Insulating film 107 is removed completely for the twice overetching. Furthermore, the silicon of active region is also etched.
Meanwhile, patterning is being miniaturized or scaled down in recent years in particular. With its scaled-down, the wiring width and depth of a source line is becoming very narrow. Each overetched portion (i.e., concave portion) 105 that serves as the source line contact is etched deep as the wiring width of the source line becomes small, thereby causing an increase in resistance value. Therefore, the conventional semiconductor memory device has the problem that upon data writing, for example, a current value is reduced so that charge retention characteristics are markedly degraded.